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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. june 2008 rev 2 1/55 55 STMPE821 8-bit xpander logic? with touchkey controller features up to 8 gpios up to 8 touchkey capacitive touch inputs operating voltage 1.8 - 5.5 v internal regulator interrupt output pin i 2 c interface 8 kv hbm esd protection 40 ff resolution, 128 steps capacitance measurement (5.0 pf dynamic range) advanced data filtering (afs) environment tracking calibration (etc) individually adjustable touch variance (tvr) setting for all channels adjustable environmental variance (evr) for optimal calibration applications mobile and smart phones portable media players game consoles description the STMPE821 is a gpio (general purpose input/output) port expander able to interface a main digital asic via the two-line bidirectional bus (i 2 c). a separate gpio expander is often used in mobile multimedia platforms to solve the problems of the limited amount of gpios typically available on the digital engine. the STMPE821 offers great flexibility, as each i/o can be configured as input, output or specific functions. the device has been designed with very low quiescent current and includes a wakeup feature for each i/o, to optimize the power consumption of the device. qfn16l (2.6x1.8mm) table 1. device summary order code package packing STMPE821qtr qfn16l (2.6 x 1.8 mm) tape and reel www.st.com
contents STMPE821 2/55 contents 1 STMPE821 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 STMPE821 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin assignment and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 STMPE821 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 capacitive compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 calibration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 noise filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 data filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 power schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 register map and function descrip tion . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 system and identificati on registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 interrupt controller module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 gpio controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 capacitive touch module register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10 basic pwm controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.1 pwm function register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.2 interrupt on basic pwm controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STMPE821 contents 3/55 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
STMPE821 functional overview STMPE821 4/55 1 STMPE821 functional overview the STMPE821 consists of the following blocks: gpio controller pwm controller impedance sensor touchkey controller i 2 c interface 1.1 STMPE821 block diagram figure 1. functional block diagram cs00046 impedance sensor i 2 c interface gpio controller touchkey controller pwm controller gpio 0 - 7 /touch 0 - 7 int rst sclk sdat aref gnd vcc vio
STMPE821 STMPE821 fu nctional overview 5/55 1.2 pin assignment and function figure 2. STMPE821 pin assignment (top view) table 2. pin assignments and function pin number pin name description 1 gpio_2/touch_2 gpio 2 2 gpio_1/touch_1 gpio 1 3 gpio_0/touch_0 gpio 0 4 aref reference capacitor for touch sensor 5 rst reset (active low) 6sdai 2 c data 7scli 2 c clock 8 int int output 9gndgnd 10 v cc supply voltage for i 2 c block 11 v io supply voltage for gpio and internal regulator 12 gpio_7/touch_7 gpio 7 13 gpio_6/touch_6 gpio 6 14 gpio_5/touch_5 gpio 5 15 gpio_4/touch_4 gpio 4 16 gpio_3/touch_3 gpio 3 c s 00045 16 15 14 1 3 5 6 7 8 12 3 4 12 11 10 9 s tmpe 8 21
STMPE821 functional overview STMPE821 6/55 1.3 STMPE821 typical application the STMPE821 is able to support up to 8 channel capacitive sensors. figure 3. typical application diagram s dat s clk int r s t aref b as e ba nd/cpu s tmpe 8 21 c s 00047
STMPE821 capacitive compensation 7/55 2 capacitive compensation the STMPE821 is capable to measuring up to 5.0 pf in capacitance difference between the reference point (zref) and the individual channels. in the case where the pcb connection between the sensor pads and the device is too long, the "reference delay" register is able to shift the reference by up to 5.0 pf, allowing the touch channels to measure added capacitance 5.0 pf with offset of 5.0 pf, as shown in following diagram. in case this is still not enou gh to compensate for the capacitan ce on sensor lines (due to very long sensor trace), an external capacitor of up to 30 pf can be connected at the a_ref pin. this allows to further shift up the dynamic range of the capacitance measurement. figure 4. capacitance compensation the sensed capacitance is accessible to host through the "impedance" registers. 2.1 calibration algorithm the STMPE821 maintains 2 parameters for each touch channel: tvr and calibrated impedance. calibrated impedance is an intern al reference of which, if the currently measured impedance exceeds the calibrated impedance by a magnitude of tvr, it is considered a touch. if the impedance is more than the calibrated impedance, but the magnitude does not exceed calibrated impedance by tvr, it is not considered a touch. in this case, 2 scenarios are possible: 1. environmental changes has caused the impedance to increase 2. finger is near the sensing pad, but not near enough in case 1, the change in impedance is expected to be small, as environmental changes are normally gradual. a value "evr" is maintained to specify the maximum impedance change that is st ill considered an en vironmental change. incre as ing c a p a cit a nce 3 0.0pf reference del a y regi s ter = 0 dyn a mic r a nge = 0 - 5.0 pf reference del a y regi s ter = 5.0 pf dyn a mic r a nge = 5.0 - 10.0 pf reference del a y = 5.0 pf aref = 3 0 pf dyn a mic r a nge = 3 5.0 - 40.0 pf 5.0 pf 5.0 pf 5.0 pf 5.0 pf 5.0 pf c s 00052
capacitive compensation STMPE821 8/55 etc wait register state a period of time of which, all touch inpu ts must remain "no touch" for the next calibration to be carried out. cal interval states the period of time between successive calibrations when there are prolonged no touch condition. 2.1.1 noise filtering when the STMPE821 is operating in the vicinity of highly emissive circuits (dc-dc converter, pwm controller/drive etc), the sensor inputs will be affected by high-frequency noise. in this situation, the time-integrating function could be used to distinguish between real touch, or emission-related false touch. the integration time and strength thres registers are used to configure the time- integrating function of STMPE821. 2.1.2 data filtering the output from t he calibration unit is an instant aneous "touch" or "no touch" status. this output is directed to the filtering stage where the touch is integrated across a programmable period of time. the output of the integration stage would be a "strength" (in strength register) that indicates the number of times a "touch" is seen, across the integration period. the "strength" is then compared with the value in "strength threshold" register. if strength exceeds the strength threshold, this is considered a final, filtered touch status. in data filtering stage, 3 modes of operation is supported: mode 1: only the ?touch? channel with highest strength is taken mode 2: all the ?touch? channels with st rength > strength threshold is taken mode 3: the 2 ?touch? channel with the highest strength is taken these modes are selected using the feature selector register. the final, filtered data is accessible through the touch byte register. table 3. calibration action under different scenarios scenario touch sensing and calibration action imp>calibrated imp + tvr touch sensing and calibration action no touch, no calibration impcalibrated imp + evr no touch, no calibration impcalibrated imp calibrated imp + change in imp imp STMPE821 capacitive compensation 9/55 2.2 power management the STMPE821 operates in 3 states. figure 5. STMPE821 operating states on reset, the STMPE821 enters the active state immediately. upon a fixed period of inactivity , the device enters into the sleep state. any touch activity in sleep state would cause the device to go back to active state. in sleep mode: -calibration continues if f2a bi t is set in control register -calibration stops if f2a bit is not set in control register (idle mode) if no touch activity is expected, the host may set the device into hibernate state to save power. active (6.5 mhz) hibernate s leep (200 khz) re s et ho s t comm a nd time o u t, ho s t comm a nd to u ch, hotkey, ho s t comm a nd ho s t comm a nd c s 000 3 9 hotkey
power schemes STMPE821 10/55 3 power schemes the STMPE821 can be powered by a 1.8 v supply directly, or 3.0 - 3.6 v supply through the internal voltage regulator. v io powers all the gpios directly, if led driving is required on the gpio, v io should be at least 3.3 v. figure 6. power using the internal regulator figure 7. power bypassing the internal regulator s tmpe 8 21 vio vcc gnd 3 - 5.5 v c s 0004 8 s tmpe 8 21 vio vcc gnd c s 00051 1.65 - 1.95 v 1.65 - 5.5 v
STMPE821 i2c interface 11/55 4 i 2 c interface the features that are supported by the i 2 c interface are the following ones: i 2 c slave device compliant to philips i 2 c specification version 2.1 supports standard (up to 100 kbps) and fast (up to 400 kbps) modes. 7-bit and 10-bit device addressing modes general call start/restart/stop i 2 c address is 0x58 (0xb0/0xb1 for write/read, including the lsb) start condition a start condition is identified by a falling edge of sdata while sclk is stable at high state. a start condition must precede any data/command transfer. the device continuously monitors for a start condition and will not respond to any transa ction unless one is encountered. stop condition a stop condition is identified by a rising edge of sdata while sclk is stable at high state. a stop condition terminates communication between the slave device and bus master. a read command that is followed by noack can be followed by a stop condition to force the slave device into idle mode. when the slave device is in idle mode, it is ready to receive the next i 2 c transaction. a stop condition at the end of a write command stops the write operation to registers. acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter releases the sdata after sending eight bits of da ta. during the ninth bit, the receiver pulls the sdata low to acknowledge the receipt of the eight bits of data. the receiver may leave the sdata in high state if it would to not acknowledge the receipt of the data. data input the device samples the data input on sdata on the rising edge of the sclk. the sdata signal must be stable during the rising edge of sclk and the sdata signal must change only when sclk is driven low. memory addressing for the bus master to communicate to the slave device, the bus master must initiate a start condition and followed by the slave device address. accompanying the slave device address, there is a read/write bit (r/w ). the bit is set to 1 for read and 0 for write operation. if a match occurs on the slave device address, the corresponding device gives an acknowledgement on the sda during the 9th bit time. if there is no match, it deselects itself from the bus by not responding to the transaction.
i2c interface STMPE821 12/55 table 4. operation modes figure 8. read and write modes (random and sequential) mode byte programming sequence read 1 start, device address, r/w = 0, register address to be read restart, device address, r/w = 1, data read, stop if no stop is issued, the data read can be continuously performed. if the register address falls within t he range that allows an address auto- increment, then the register addres s auto-increments internally after every byte of data being read. for those register addresses that fall within a non-incremental address range , the address will be kept static throughout the entire write operations. refer to the memory map table for the address ranges that are auto and non-increment. an example of such a non-increment address is fifo write 1 start, device address, r/w = 0, register address to be written, data write, stop if no stop is issued, the data writ e can be continuously performed. if the register address falls within the range that allows address auto- increment, then the register addres s auto-increments internally after every byte of data being written in. for those register addresses that fall within a non-incremental address range, the address will be kept static throughout the entire write operations. refer to the memory map table for the address ranges that are auto and non-increment. an example of a non-increment address is data port for initializing the pwm commands. start r/w=0 ack device address reg address ack restart device address ack r/w=1 data read no ack stop one byte read start r/w=0 ack device address reg address ack restart device address ack r/w=1 data read ack more than one byte read ack no ack stop data read + 1 data read + 2 start r/w=0 ack device address reg address ack data to be written ack stop one byte write more than one byte read start r/w=0 ack device address reg address ack data to write ack stop data to write + 2 ack ack data to write + 1 master slave
STMPE821 register map and function description 13/55 5 register map and function description this section lists and describes the registers of the STMPE821 device, starting with a register map and then provides detailed descriptions of register types. table 5. register summary map table address register name bit type reset value function 0x00 chip_id_0 8 r 0x08 device identification 0x01 chip_id_1 8 r 0x21 device identification 0x02 id_ver 8 r 0x01 revision number 0x03 sys_cfg_1 8 r/w 0x00 syst em configuration 1 0x04 sys_cfg_2 8 r/w 0xef system configuration 2 0x08 int_ctrl 8 r/w 0x01 interrupt control register 0x09 int_en 8 r/w 0x01 interrupt enable register 0x0a int_sta 8 r 0x01 interrupt status register 0x0b gpio__int_en_lsb 8 r/w 0x00 gpio interrupt enable register 0x0c gpio__int_en_msb 8 r/w 0x00 g pio interrupt enable register 0x0d gpio_int_sta_lsb 8 r/w 0x00 gp io interrupt status register 0x0e gpio_int_sta_msb 8 r/w 0x00 gpio interrupt status register 0x10 gpio_mr 8 r/w 0x00 gpio monitor pin 0x12 gpio_set 8 r/w 0x00 gpio set pin state register 0x14 gpio_dir 8 r/w 0x00 gpio set pin direction register 0x16 gpio_funct 8 r/w 0x00 gpio function register 0x18 touch_fifo 64 r 0x00 fifo access for touch data buffer 0x20 feature_sel 8 r/w 0x04 feature selection 0x21 etc_wait 8 r/w 0x27 wait time 0x22 cal_interval 8 r/w 0x30 calibration interval 0x23 integration_ time 8 r/w 0x0f integration time 0x25 ctrl 8 r/w 0x00 control 0x26 int_mask 8 r/w 0x08 interrupt mask 0x27 int_clr 8 r/w 0x00 interrupt clear 0x28 filter_period 8 r/w 0x00 filter period 0x29 filter_threshol d 8 r/w 0x00 filter threshold 0x2a ref_dly 8 r/w 0x00 reference delay 0x30 - 0x37 tvr 8 r/w 0x08 touch variance setting
register map and function description STMPE821 14/55 0x40 evr 8 r/w 0x04 enviromental variance 0x50 - 0x57 strength_thres [0-7] 8 r/w 0x01 setting of strength threshold for each channel 0x60 - 0x67 strength [0-7] 8 r 0x00 strenght 0x70 - 0x77 cal_impedance [0-7] 8 r 0x00 calibrated impedance 0x80 - 0x87 impedance [0-7] 8 r 0x00 impedance 0x90 touch_byte_l 8 r 0x00 touch sensing data output 0x91 touch_byte_h 8 r 0x00 touch sensing data output 0x92 int_pending 8 r/w 0x00 status of gint interrupt sources 0xa0 pwm_off_output 8 r/w 0x00 pwm group control 0xa1 master_en 8 r/w 0x00 master enable 0xb0 pwm0_set 8 r/w 0x00 pwm 0 setup 0xb1 pwm0_ctrl 8 r/w 0x00 pwm 0 control 0xb2 pwm0_ramp_rate 8 r/w 0x00 pwm 0 ramp rate 0xb4 pwm1_set 8 r/w 0x00 pwm 1 setup 0xb5 pwm1_ctrl 8 r/w 0x00 pwm 1 control 0xb6 pwm1_ramp_rate 8 r/w 0x00 pwm 1 ramp rate 0xb8 pwm2_set 8 r/w 0x00 pwm 2 setup 0xb9 pwm2_ctrl 8 r/w 0x00 pwm 2 control 0xba pwm2_ramp_rate 8 r/w 0x00 pwm 2 ramp rate 0xbc pwm3_set 8 r/w 0x00 pwm 3 setup 0xbd pwm3_ctrl 8 r/w 0x00 pwm 3 control 0xbe pwm3_ramp_rate 8 r/w 0x00 pwm 3 ramp rate table 5. register summary map table (continued) address register name bit type reset value function
STMPE821 system and identification registers 15/55 6 system and identification registers table 6. system and identification registers map chip_id_x device identification address: 0x00, 0x01 type: r reset: 0x08, 0x21 description: 16-bit device identification id_ver revision number address: 0x02 type: r reset: 0x01 description: 16-bit revision number address register name bit type reset function 0x00 chip_id_0 16 r 0x08 device identification 0x01 chip_id_1 16 r 0x21 device identification 0x02 id_ver 8 r 0x01 revision number 0x03 sys_cfg_1 8 r/w 0x00 system configuration 1 0x04 sys_cfg_2 8 r/w 0xef system configuration 2
system and identification registers STMPE821 16/55 sys_cfg_1 system configuration 1 address: 0x03 type: r/w reset: 0x00 description: the reset control register enables to reset the device sys_cfg_2 system configuration 2 address: 0x04 type: r/w reset: 0xef description: this register enables to switch off the clock supply 76543 2 1 0 reserved sleep warm_reset soft_reset hibernate [7:4] reserved [3] sleep : write ?1? to enable sleep mode [2] warm_reset : write ?1? to initiate a warm reset. regi ster content remains, state machine reset. [1] soft_reset : write ?1? to initiate a soft reset. all re gisters content and state machines reset. [0] hibernate : force the device into hibernation mode. write ?1? to enter the hibernate mode, 76543 2 1 0 sensor clock 2 sensor clock 1 sensor clock 0 ? pwm clock disable gpio clock disable fifo clock disable touch clock disable [7:5] sensor clock : see description in the table below. [4] reserved [3] pwm clock disable : write ?1? to disable the clock to pwm unit. [2] gpio clock disable : write ?1? to disable the clock to gpio unit. note that gpio clock is required for pwm operation. [1] fifo clock disable : write ?1? to disable the clock to fifo unit. this must be set to ?0? if touch interrupt is required. [0] touch clock disable : write ?1? to disable the clock to touch unit.
STMPE821 system and identification registers 17/55 table 7. sensor clock setting mode divider sensor clock [2:0] active calibration idle operational (6.5 mhz) 1 000 12.8 khz 100 khz 400 hz 2 001 6.4 khz 50 khz 200 hz 4 010 3.2 khz 25 khz 100 hz 8 011 1.6 khz 12.5 khz 50 hz 16 1xx 800 kz 6.25 khz 25 hz autosleep (200 khz) 1 000 400 hz 3.2 khz 12.5 hz 2 001 200 hz 1.6 khz 6.2 hz 4 010 100 hz 800 hz 3.1 hz 8 011 50 hz 400 hz 1.5 hz 16 1xx 25 hz 200 hz 0.75 hz
interrupt controller module STMPE821 18/55 7 interrupt controller module figure 9. interrupt controller module block diagram interr u pt en ab le interr u pt s t a t us and int and int m as k int pending gpio interr u pt s t a t us gpio interr u pt en ab le c s 0005 3
STMPE821 interrupt controller module 19/55 int_ctrl interrupt control register address: 0x08 type: r/w reset: 0x00 description: this register is used to enable control th e polarity, edge/level and enabling of the interrupt system.device 76543210 polarity type int_en [7:3] reserved [2] polarity : '0' for active low '1' for active high [1] type : '0' for level trigger '1' for edge trigger (pulse width is 200 us) [0] int_en : '0' to disable all interrupt '1' to enable all interrupt
interrupt controller module STMPE821 20/55 int_en interrupt enable register address: 0x09 type: r/w reset: 0x00 description: this register is used to enable the interruption from a system related interrupt source to the host. writing ?1? in this register enables the corresponding interrupt event to generate interrupt signal at the int pin. note that even if the interrupt is not enabled, an interrupt event will still be reflecte d in the interrupt status register. 76543 2 1 0 gpio pwm3 pwm2 pwm1 pwm0 gen fifo por [7] gpio : one or more level transition in enabled gpios [6] pwm3: completion of pwm sequence [5] pwm2 : completion of pwm sequence [4] pwm1 : completion of pwm sequence [3] pwm0 : completion of pwm sequence [2] gen : system int (a21, i2a, eoc) [1] fifo : data available in fifo [0] por : power-on reset
STMPE821 interrupt controller module 21/55 int_sta interrupt status register address: 0x0a type: r reset: 0x00 description: this register is used to enable the interruption from a system related interrupt source to the host. regardle ss whether the iesysior bits are enabled, the issysior bits are still updated. writing ?1? cl ears a bit in this register . writing ?0? has no effect. 76543 2 1 0 gpio pwm3 pwm2 pwm1 pwm0 gen fifo por [7] gpio : one or more level transition in enabled gpios [6] pwm3: completion of pwm sequence [5] pwm2 : completion of pwm sequence [4] pwm1 : completion of pwm sequence [3] pwm0 : completion of pwm sequence [2] gen : system int (a21, i2a, eoc) [1] fifo : data available in fifo [0] por : power-on reset
interrupt controller module STMPE821 22/55 gpio_int_en gpio interr upt enable registeri address: 0x0b, 0x0c type: r/w reset: 0x00 description: the gpio interrupt enable register is used to enable the interruption from a particular gpio interrupt source to the host. the ieg[7:0] bits and the interrupt enable mask bits correspond to the gpio[7:0} pins. gpio_int_sta gpio inte rrupt status register address: 0x0d type: r/w reset: 0x00 description: the gpio interrupt status register lsb monitors the status of the interruption from a particular gpio pin interrupt source to the host. regardless whether the iegpior bits are enabled or not, the int_sta_gpio _lsb bits are still updated. the isg[7:0] bits are the interrupt status bits correspond to the gpio[7:0] pins. 76543 2 1 0 ieg[x] [7:0] ieg[7:0] interrupt enable gpio mask (where x = 7 to 0) writing a ?1? to the ie[x] bit will enable the interruption to the host. 76543 2 1 0 [7:0] isg[x] : interrupt status gpio (where x = 7 to 0) read: interrupt status of the gpio[x]. writing ?1? clears a bit. writing ?0? has no effect.
STMPE821 gpio controller 23/55 8 gpio controller a total of 8 gpios are available in the STMPE821. the gpio controller contains the registers that allow the host system to configure each of the pins into either a gpio, direct output of a touch channel or a pwm output. unused gpios should be configured as outputs to minimize the power consumption. a group of registers is used to control the exact function of each of the 8 gpios. the registers and their respective address is listed in the following table. all gpio registers are named as gpxx, where: xxx represents the functional group for lsb registers: for msb registers: table 8. gpio controller registers summary map address register name description auto-increment 0x10 gpio_mr_lsb gpio monitor pin state register yes 0x11 gpio_mr_msb 0x12 gpio_set_lsb gpio set pin state register yes 0x13 gpio_set_msb 0x14 gpio_dir_lsb gpio set pin direction register yes 0x15 gpio_dir_msb 0x16 gpio_funct_lsb gpio function register yes 0x17 gpio_funct_msb 76543 2 1 0 io-7 io-6 io-5 io-4 io-3 io-2 io-1 io-0 76543 2 1 0 reserved
gpio controller STMPE821 24/55 the function of each bit is shown in the following table: table 9. gpio control bits function register name function gpio monitor pin state reading this bit yields the current state of the bit. writing has no effect. gpio set pin state writing '1' to this bit causes the corresponding gpio to go to '1' state writing '0' to this bit causes the corresponding gpio to go to '0' state gpio set pin direction '0' sets the corresponding gpio to input state, and '1' sets it to output state. all bits are '0' on reset. the gpio must be set as output if the pwm on this pin is to be used. gpio function '1' sets the corresponding gpio to function as gpio/pwm, and '0' sets it to touchkey direct output mode. for gpio 0-3, if the gpio function is set to gpio/pwm mode and the af bits in the pwm master enab le register is enabled, the corresponding gpio will function as pwm output.
STMPE821 capacitive touch module registers 25/55 9 capacitive touch module registers touch_fifo touch fifo address: 0x19, 0x18 type: r reset: 0x00 description: touch_fifo is the access port for the internal 4-level fifo used for buffering the touch events. while it is possible to access each bytes in the data structure directly, it is recommended that the fifo is accessed only via the 0x18 address. the fifo must be accessed in multiples of 2 bytes (lsb, msb). for STMPE821, msb is reserved and lsb contains a snapshot of the recent touch event. the fifo must be accessed in multiples of 2 bytes (lsb, msb). for STMPE821, msb is reserved and lsb contains a snapshot of the recent touch event. where tn is touch status of touch sensing channel n. table 10. touch_fifo summary table address function 0x18 fifo-0, lsb 0x19 fifo-0, msb 0x1a fifo-1, lsb 0x1b fifo-1, msb 0x1c fifo-2, lsb 0x1d fifo-2, msb 0x1e fifo-3, lsb 0x1f fifo-3, msb 76543 2 1 0 t7 t6 t5 t4 t3 t2 t1 t0
capacitive touch module registers STMPE821 26/55 feature_select feature select address: 0x20 type: r/w reset: 0x04 description: controls afs (advanced filtering syste m and second level filtering feature etc_wait wait time setting address: 0x21 type: r/w reset: 0x27 description: sets the wait time between the calibration and the last button touch 76543 2 1 0 reserved afs3 afs2 afs1 filter en [7:4] reserved [3] afs3 : write '1' to enable afs mode 3 [2] afs2 : write '1' to enable afs mode 2 [1] afs1 : write '1' to enable afs mode 1 [0] filter en : write '1' to enable filter 76543 2 1 0 etc_wait[7:0] [7:0] etc_wait[7:0] : etc wait time = etc_wait[7:0] *64 + sensor clock period a "non-touch" condition must persist for this wait time, before an etc operation is carried out. range: 800 ms - 12.8 s
STMPE821 capacitive touch module registers 27/55 cal_interval calibration interval address: 0x22 type: r/w reset: 0x30 description: calibration interval 76543 2 1 0 cal_interval [7:0] calibration interval : interval between calibration = calibration interval [7:0] * sensor clock period * 50 range: 625 ms - 10 s
capacitive touch module registers STMPE821 28/55 integration time integration time address: 0x23 type: r/w reset: 0x0f description: integration time 76543 2 1 0 integration_time[7:0] [7:0] integration time in afs mode total period of integration = sensor clock period * integration time [7:0] 50us - 800us
STMPE821 capacitive touch module registers 29/55 ctrl control address: 0x25 type: r/w reset: 0x00 description: control 76543 2 1 0 reserved f2a hdc_u hdc_c hold [7:4] 0x90 [3] f2a : write '1' to force device to remain in active state at all times [2] hdc_u : write '1' to perform unconditional host driven calibration. cleared to '0' when calibration is completed only applicable hold is '1' [1] hdc_c : write '1' to perform conditional host driven calibration. calibration is performed if and only if no touch is detected. cleared to '0' when calibration is completed only applicable hold is '1' [0] hold : '0' to enable etc '1' to disable etc
capacitive touch module registers STMPE821 30/55 int_mask interrupt mask address: 0x26 type: r/w reset: 0x08 description: writing '1' to this register disables the corresponding interrupt source. 76543 2 1 0 reserved eoc i2a a2i reserved [7:4] reserved [3] eoc : end of calibration this interrupt occurs on both automatic and forced calibration [2] i2a : sleep to active transition [1] a2i : active to sleep transition [0] reserved
STMPE821 capacitive touch module registers 31/55 int_clr interrupt clear address: 0x27 type: r/w reset: 0x00 description: writing '1' to this register clears the corresponding interrupt source in int_pending register. 76543 2 1 0 reserved eoc i2a a2i reserved [7:4] 0x90 [3] eoc : end of calibration this interrupt occurs on both automatic and forced calibration [2] i2a : sleep to active transition [1] a2i : active to sleep transition [0] reserved
capacitive touch module registers STMPE821 32/55 filter_period filter period address: 0x28 type: r/w reset: 0x00 description: filter period. 76543 2 1 0 filter_count [7:0] filter_count : additional filter to stabilize touch output in afs mode. afs touch output is monitored for filter count [7:0] times every integration time. for each time a "touch status" is detec ted, an internal "filter counter" is incremented once. this counter value is then compared with filter threshold (register 0x3e)
STMPE821 capacitive touch module registers 33/55 filter_threshold fi lter threshold address: 0x29 type: r/w reset: 0x00 description: filter threshold. reference_delay reference delay address: 0x2a type: r/w reset: 0x00 description: shifting of capacitive sensor dynamic ra nge. the capacitance value set into this register is in effect, equivalent to capacitor connected to the s_ref pin. 76543 2 1 0 filter_threshold [7:0] filter_threshold : an internal "filter counter" is compared with filter threshold [7:0] to determine if a valid touch has occurred. 76543 2 1 0 reserved reference_delay [7] reserved [6:0] reference_delay : valid range = 0-127 each step represents capa citance value of 0.06 pf warm reset is required after this value is updated
capacitive touch module registers STMPE821 34/55 tvr touch variance setting address: 0x30 - 0x3b type: r/w reset: 0x08 description: touch variance setting. 76543 2 1 0 reserved tvr [7] reserved [6:0] tvr : setting tvr between 0-99 a high tvr value decreases sensitivity of the sensor, but increasing its tolerance to ambient noise a small tvr value increases the sensitivity.
STMPE821 capacitive touch module registers 35/55 evr enviromental variance address: 0x40 type: r/w reset: 0x04 description: enviromental variance setting. 76543 2 1 0 reserved tvr [7] reserved [6] evr : evr is used to detect "non-touch" condition
capacitive touch module registers STMPE821 36/55 strength_threshold st rength threshold address: 0x50 - 0x5b type: r/w reset: 0x01 description: strength threshold. strength strength address: 0x60 - 0x67 type: r reset: 0x00 description: the number of times where a sense capacitance exceeds the calibrated reference impedance 76543 2 1 0 strength_threshold [7:0] strength_threshold : setting threshold to be used in afs mode to determine valid touch 76543210 strength [7:0] strength : read-only field counts the number of times a sensed impedance exceeds calibrated reference impedance over and integration time. maximum strength equals integration time [7:0]
STMPE821 capacitive touch module registers 37/55 calibrated_impedance calibrated impedance address: 0x70 - 0x77 type: r reset: 0x00 description: calibrated impedance is an integral reference value maintained by the device. impedance impedance address: 0x80 - 0x87 type: r reset: 0x00 description: impedance is the instantaneous impedance value seen at the input pin of eac cap. sensing pin. 76543210 cal_impedance [7:0] calibrated impedance : calibrated reference impedance 76543210 impedance [7:0] impedance : currently sensed impedance
capacitive touch module registers STMPE821 38/55 touch_byte_l touch byte l address: 0x90 type: r reset: 0x00 description: touch status of capacitive channel 0 - 7. 76543210 touch [7:0] touch : reads '1' if the corresponding capacitance sensing channel reads a valid touch
STMPE821 capacitive touch module registers 39/55 touch_byte_h touch byte h address: 0x91 type: r reset: 0x00 description: reserved. 76543210 reserved [7:0] reserved:
capacitive touch module registers STMPE821 40/55 int_pending interrupt pending address: 0x92 type: r/w reset: 0x00 description: reflects the status of each interrupt source. 76543210 reserved eoc i2a a21 reserved [7:4] reserved [3] eoc : end of calibration [2] i2a : sleep to active transition [1] a21 : active to sleep transition [0] reserved
STMPE821 basic pwm controller 41/55 10 basic pwm controller the advanced pwm allows complex brightness and blinking control of a led. the basic pwm controller allows simple r brightness control and basic blinking patterns. the STMPE821 is fitted with a 4-channel basic pwm controller. the pwm controllers outputs are connected to the gpio 0-3. in order to activate the pwm channels, the alternate function bits in the master enable register must be set to '1'. the pwm controllers are capable of generating the following brightness patterns: figure 10. pulses with programmable br ightness, on/off period and repetition on period = period 0[1:0] * time unit [3:0] off period = period 1[1:0] * time unit [3:0] duty cycle during ?on peri od? = brightness [7:4] number of cycles = repetition [3:0] ramp mode is disabled figure 11. ramps with programmable brightness, on/off period and repetition d u ty cycle time on period off period on period off period 1 time u nit c s 00054 duty cycle time on period off period on period off period 1 time unit c s 00055
basic pwm controller STMPE821 42/55 ?on? period = period 0[1:0] * time unit [3:0] ?off? period = period 1[1:0] * time unit [3:0] duty cycle during ?on? period = brightness [7:4] number of cycles = repetition [3:0] ramp up rate is programmable. figure 12. fixed brightness output ?on? period = period 0[1:0] * time unit [3:0] off period = don't care duty cycle during ?on? period = brightness [7:4] number of cycles = repetition [3:0] = 0 (means infinite repetition) duty cycle time time unit c s 00056
STMPE821 basic pwm controller 43/55 10.1 pwm function register map master_en master enabler address: 0xa1 type: r/w reset: 0x00 description: write ?1? to select pwm function on the corresponding channel. table 11. pwm function register map summary table register name description auto-increment (during sequential r/w) pwm_off_output set the output level when pwm is disabled ye s master_en enables/disables individual basic pwm channels ye s pwm0_set pwm 0 setup yes pwm0_ctrl pwm 0 control yes pwm0_ramp_rate pwm 0 ramp rate yes pwm1_set pwm 1 setup yes pwm1_ctrl pwm 1 control yes ramp1_rate pwm 1 ramp rate yes pwm2_set pwm 2 setup yes pwm2_ctrl pwm 2 control yes ramp2_rate pwm 2 ramp rate yes pwm3_set pwm 3 setup yes pwm3_ctrl pwm 3 control yes pwm3_rate pwm 3 ramp rate yes 76543210 af3 af2 af2 af0 en3 en2 en1 en0 [7:4] af3:0 [3:0] out3:0 : default is '0'. write ?1? to used the corresponding pwm channel mu st be diabled for the controlling registers to be accessed.
basic pwm controller STMPE821 44/55 pwm_off_output pwm group control register address: 0xa0 type: r/w reset: 0x00 description: pwm group control register. ramp_rate ramp rate register address: 0xb2 type: r/w reset: 0x00 description: ramp rate register. 76543210 out3 out2 out1 out0 [7:4] reserved [3:0] out3:0 : default is '0' '1' - pwm channel outputs '1' when disabled '0' - pwm channel outputs '0' when disabled 76543210 reserved ramp_down ramp_up [7:6] reserved [5:3] ramp_down [2:0] : '000' = 1/4 of time unit per brightness level change '001' = 1/8 of time unit per brightness level change '010' = 1/16 of time unit per brightness level change '011' = 1/32 of time unit per brightness level change '100' = 1/64 of time unit per brightness level change '101' = 1/128 of time unit per brightness level change '110' = reserved '111' = reserved [2:0] ramp_up [2:0] : '000' = 1/4 of time unit per brightness level change '001' = 1/8 of time unit per brightness level change '010' = 1/16 of time unit per brightness level change '011' = 1/32 of time unit per brightness level change '100' = 1/64 of time unit per brightness level change '101' = 1/128 of time unit per brightness level change '110' = reserved '111' = reserved
STMPE821 basic pwm controller 45/55 pwm_n_setup pwm_n setup register (n=0-3) address: 0xb0 type: r/w reset: 0x00 description: pwm setup register. 76543210 brightness timing [7:4] brightness: this defines the duty cycle during the on peri od of the pwm channel output which in turn determines the brightness level of t he led that the pwm output drives. 0000: duty cycle ratio 1:15 ( 6.25%, minimum brightness) 0001: duty cycle ratio 2:14 ( 12.50%) 0010: duty cycle ratio 3:13 ( 18.75%) 0011: duty cycle ratio 4:12 ( 25.00%) 0100: duty cycle ratio 5:11 ( 31.25%) 0101: duty cycle ratio 6:10 ( 37.50%) 0110: duty cycle ratio 7: 9 ( 43.75%) 0111: duty cycle ratio 8: 8 ( 50.00%) 1000: duty cycle ratio 9: 7 ( 56.25%) 1001: duty cycle ratio 10: 6 ( 62.50%) 1010: duty cycle ratio 11: 5 ( 68.75%) 1011: duty cycle ratio 12: 4 ( 75.00%) 1100: duty cycle ratio 13: 3 ( 81.25%) 1101: duty cycle ratio 14: 2 ( 87.50%) 1110: duty cycle ratio 15: 1 ( 93.75%) 1111: duty cycle ratio 16: 0 (100.00%, maximum brightness) [3:1] timing [3:0] is the time unit from which the dur ation of the on period and off period is defined in: "000" = 20 ms "001" = 40 ms "010" = 80 ms "011" = 160 ms "100" = 320 ms "101" = 640 ms "110" = 1280 ms "111" = 2560 ms [0] write '1' to activate ramp mode
basic pwm controller STMPE821 46/55 pwm_ctrl_n pwm control register n=0-3 address: 0xb1, 0xb5, 0xb9, 0xbd type: r/w reset: 0x00 description: this register controls the sequence and repetition of blinking. 76543210 period_0 period_1 repetition frame_order [7:6] period_0 : this defines the on period time which is when the pwm channel output is toggling. the time unit is as defined in the timing bits of the respective timing_setup registers: 00: 1 time unit 01: 2 time unit 10: 3 time unit 11: 4 time unit [5:4] period_1 : this defines the off period time which is when the pwm channel output is low, that is, not toggling. the time unit is as defined in the timing bits of the respective timing_setup registers: 00: 0 time unit. this means that there is no of f period but only on period, that is, the pwm channel output will always be toggling. 01: 1 time unit 10: 2 time unit 11: 3 time unit [3:1] repetition : this defines the number of repetition of pairs of period_0 and period_1. 000: infinite repetition. 001: execute only one pair. 010: execute 2 pairs 011: execute 3 pairs 100: execute 4 pairs 101: execute 5 pairs 110: execute 6 pairs 111: execute 7 pairs [0] frame_order : for pwm mode, this defines which fram e, period_0 or period_1 comes first. 0: period_0 is outputte d first then period_1. 1: period_1 is outputte d first then period_0.
STMPE821 basic pwm controller 47/55 10.2 interrupt on basic pwm controller the basic pwm controller can be programmed to generate interrupts on completion of the blinking sequence. a) each basic pwm controller has its own bit in interrupt the enable/status registers. b) if enabled, completion in any of the pw m controller triggers interrupts. no interrupt is generated if infinite repetition is set.
maximum rating STMPE821 48/55 11 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 12. absolute maximum ratings symbol parameter value unit min typ max v cc power supply 2.5 v v io gpio supply voltage 6.0 v v esd esd protection on each gpio/touch pin 8 kv
STMPE821 electrical specifications 49/55 12 electrical specifications table 13. dc electrical characteristics (-40 ? 85 c unless otherwise stated) ) symbol parameter test condition value unit min typ max v cc core supply voltage 1.65 ? 1.95 v v io io supply voltage 1.65 ? 5.5 v i active active current 5% touch activity 42 63 a i active active current 10% touch activity 60 90 a i active active current 100% touch activity 350 550 a i sleep sleep current 25 40 a i hibernate hibernate current 4 7 a v il input voltage low state (reset/i 2 c) v cc = 1.8 v -0.3 v 0.35 v cc v v ih input voltage high state (reset/i 2 c) v cc =1.8v 0.65v cc v cc +0.3 v v v il input voltage low state (gpio) v io =1.8 ? 5.0 v -0.3 v io 0.35 v io v v ih input voltage high state (gpio) v io =1.8 ? 5.0 v 0.65 v io v io +0.3 v v v ol output voltage low state (gpio) v io = 1.8 v, i ol =4ma -0.3 v 0.25 v io v v oh output voltage high state (gpio) v io = 1.8 v, i ol =4ma 0.75 v io v io +0.3 v v v ol output voltage low state (gpio) v io =3.3 ? 5.0 v, i ol =8ma -0.3 v 0.25 v io v v oh output voltage high state (gpio) v io =3.3 ? 5.0 v, i ol =8ma 0.75 v io v io +0.3 v v i leakage input leakage current v in = 5.5 v, v io =5.5v all gpios 0.05 0.5 a
package mechanical data STMPE821 50/55 13 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com . figure 13. qfn16l (2.6 x 1.8 mm) package outline 1. drawing not to scale. 2. dimensions are in millimeters. bottom view qfn16l
STMPE821 package mechanical data 51/55 figure 14. qfn16l (2.6 x 1.8 mm) footprint recommentations 1. drawing not to scale. 2. dimensions are in millimeters. table 14. qfn16l (2.6 x 1.8 mm) mechanical data symbol millimeters typ min max a 0.55 0.45 0.60 a1 0.02 0 0.05 b 0.20 0.15 0.25 d 2.60 2.50 2.70 e 1.80 1.70 1.90 e 0.40 l 0.40 0.35 0.45 7874009
package mechanical data STMPE821 52/55 figure 15. qfn16l (2.6 x 1.8 mm) carrier tape 7 8 597 8 -j
STMPE821 package mechanical data 53/55 figure 16. qfn16l (2.6 x 1 .8 mm) reel information 1. drawing not to scale. 2. dimensions are in millimeters 7 8 7597 8
revision history STMPE821 54/55 14 revision history table 15. document revision history date revision changes 26-feb-2008 1 initial release. 10-jun-2008 2 modified: operating voltage range so as to included support for 5.5 v, section 1.3 on page 6 , figure 5 on page 9 , section 4 on page 11 , section 5 on page 13 , section 8 on page 23 , added: pwm_ctrl_n register description and i leakage value in table 13 on page 49
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